MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 583

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.3.7
TDR configures the operation of the hardware breakpoint logic that corresponds with the
ABHR/ABLR/AATR, PBR/PBR1/PBR2/PBR3/PBMR, and DBR/DBMR registers within the debug
module. TDR controls the actions taken under the defined conditions. Breakpoint logic may be configured
as one- or two-level trigger. TDR[31–16] defines the second-level trigger, and TDR[15–0] defines the
first-level trigger.
Freescale Semiconductor
31–16
14–13
12–11
Field
TMM
SZM
10–8
TTM
6–5
4–3
2–0
RM
TM
SZ
TT
15
R
7
Trigger Definition Register (TDR)
Reserved, must be cleared.
Read/write mask. Masks the R bit in address comparisons.
Size mask. Masks the corresponding SZ bit in address comparisons.
Transfer type mask. Masks the corresponding TT bit in address comparisons.
Transfer modifier mask. Masks the corresponding TM bit in address comparisons.
Read/write. R is compared with the R/W signal of the processor’s local bus.
Size. Compared to the processor’s local bus size signals.
00 Longword
01 Byte
10 Word
11 Reserved
Transfer type. Compared with the local bus transfer type signals. These bits also define the TT encoding for
BDM memory commands.
00
Else Reserved
Transfer modifier. Compared with the local bus transfer modifier signals, which give supplemental information
for each transfer type. These bits also define the TM encoding for BDM memory commands (for backward
compatibility).
000 Reserved
001 User-mode data access
010 User-mode code access
011 Reserved
100 Reserved
101 Supervisor-mode data access
110 Supervisor-mode code access
111 Reserved
The debug module has no hardware interlocks. To prevent spurious
breakpoint triggers while the breakpoint registers are being loaded, disable
TDR (clear TDR[L2EBL,L1EBL]) before defining triggers.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Normal processor access
Table 26-13. AATR Field Descriptions
NOTE
Description
Version 1 ColdFire Debug (CF1_DEBUG)
26-19