MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 239

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

All ColdFire processors support a 1024-byte vector table aligned on any 1-MB address boundary. For the
V1 ColdFire core, the only practical locations for the vector table are based at 0x(00)00_0000 in the flash
or 0x(00)80_0000 in the RAM. The table contains 256 exception vectors; the first 64 are reserved for
internal processor exceptions, and the remaining 192 are device-specific interrupt vectors. The IRQ
assignment table is partially populated depending on the exact set of peripherals for the given device.
The exception vector table for MCF51EM256 series devices is shown in
Freescale Semiconductor
Number(s)
4. The processor calculates the address of the first instruction of the exception handler. By definition,
Vector
2–63
64
65
66
67
68
69
70
71
72
73
74
0
1
type determines whether the program counter placed in the exception stack frame defines the
location of the faulting instruction (fault) or the address of the next instruction to be executed
(next). For interrupts, the stacked PC is always the address of the next instruction to be executed.
the exception vector table is aligned on a 1MB boundary. This instruction address is generated by
fetching a 32-bit exception vector from the table located at the address defined in the vector base
register (VBR). The index into the exception table is calculated as (4 × vector number). After the
exception vector has been fetched, the contents of the vector serves as a 32-bit pointer to the
address of the first instruction of the desired handler. After the instruction fetch for the first opcode
of the handler has been initiated, exception processing terminates and normal instruction
processing continues in the handler.
INTC_PL6P7
INTC_PL6P6
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Interrupt
Number
Source
10
—
—
—
0
1
2
3
4
5
6
7
8
9
Table 10-2. MCF51EM256/128 Exception Vector Table
0x008–0x0FC
Address
Vector
Offset
0x10C
0x11C
0x000
0x004
0x100
0x104
0x108
0x110
0x114
0x118
0x120
0x124
0x128
Interrupt
Level
—
—
—
7
7
7
7
6
6
6
6
6
6
6
5
5
Priority
within
Level
N/A
N/A
N/A
mid
3
2
1
7
6
5
4
3
2
1
7
6
Program
Stacked
Counter
Next
Next
Next
Next
Next
Next
Next
Next
Next
Next
Next
—
—
—
Table
Reserved for remapped vector #1
Reserved for remapped vector #2
Initial supervisor stack pointer
Reserved for internal CPU
Initial program counter
10-2.
Low_voltage_detect
Interrupt Controller (CF1_INTC)
Assignment
MTIM2_ovfl
MTIM3_ovfl
exceptions
PDB_ERR
TPM1_ch0
TPM1_ch1
TPM1_ovfl
Reserved
Reserved
IRQ_pin
PDB
10-3