MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 381

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The TPM may be used in an 8-bit MCU. The settings in the timer channel registers are buffered to ensure
coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers
TPMMODH, TPMMODL, TPMCnVH, and TPMCnVL, actually write to buffer registers.
In center-aligned PWM mode, the TPMCnVH:L registers are updated with the value of their write buffer
according to the value of CLKS bits, so:
When TPMCNTH:TPMCNTL=TPMMODH:TPMMODL, the TPM can optionally generate a TOF
interrupt (at the end of this count).
Writing to TPMSC cancels any values written to TPMMODH and/or TPMMODL and resets the
coherency mechanism for the modulo registers. Writing to TPMCnSC cancels any values written to the
channel value registers and resets the coherency mechanism for TPMCnVH:TPMCnVL.
16.5
16.5.1
The TPM is reset whenever any MCU reset occurs.
16.5.2
Reset clears the TPMSC register which disables clocks to the TPM and disables timer overflow interrupts
(TOIE=0). CPWMS, MSnB, MSnA, ELSnB, and ELSnA are all cleared which configures all TPM
channels for input-capture operation with the associated pins disconnected from I/O pin logic (so all MCU
pins related to the TPM revert to general purpose I/O pins).
16.6
16.6.1
The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel.
The meaning of channel interrupts depends on each channel’s mode of operation. If the channel is
configured for input capture, the interrupt flag is set each time the selected input capture edge is
recognized. If the channel is configured for output compare or PWM modes, the interrupt flag is set each
time the main timer counter matches the value in the 16-bit channel value register.
All TPM interrupts are listed in
that can block the interrupt request from leaving the TPM and getting recognized by the separate interrupt
processing logic.
Freescale Semiconductor
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If (CLKS[1:0] = 00), the registers are updated when the second byte is written
If (CLKS[1:0] not = 00), the registers are updated after the both bytes were written, and the TPM
counter changes from (TPMMODH:TPMMODL - 1) to (TPMMODH:TPMMODL). If the TPM
counter is a free-running counter, the update is made when the TPM counter changes from 0xFFFE
to 0xFFFF.
Reset Overview
Interrupts
General
Description of Reset Operation
General
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table 16-8
which shows the interrupt name, the name of any local enable
Timer/PWM Module(TPM)
16-19