MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 403

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

This register indicates the status of various processes going inside the IRTC. Status of crystal or
temperature compensation can be obtained. This register also helps the MCU to read time or date register
when their values are stable and not changing. Software reset resets the register to its default state. Done
bits get cleared on read.
Freescale Semiconductor
C_DON
BERR
INVAL
OCAL
WPE
CLV
5
4
3
2
1
0
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
CPU Low Voltage. This read-only bit is asserted when the MCU/CPU power falls below the read only
threshold when all write cycles are terminated normally and no change is done to the registers.This bit
is read-only and self-cleared. It is set when the V
cleared when the V
writable.
Write Protect Enable. Indicates that registers are in locked mode and write to registers is disabled. Any
write access made to the register space is ignored when write protection is enabled (i.e. registers in
locked mode).
Calibration Output Bit or Compensation Interval Bit. This status bit is asserted for a time equal to
compensation interval seconds. This bit is used by MCU to calculate the interrupts serviced during this
interval and perform corrections in case of deviations. This bit toggles on every compensation interval
start and is either 0 or 1 during the entire duration. This bit will not toggle if compensation logic has been
disabled by MCU. This bit is same as the irtc_cal_out signal output from IRTC.
Bus Error. Indicates that a read or write cycle was started by MCU when the INVAL bit is set. Write
access to time/date registers gets nullified (terminate normally) and no register value gets changed.
Read during INVAL bit asserted returns 16’hFFFF. No Transfer Error is asserted.
Compensation Done. Read only bit gets cleared by writing 1 to it.
‘1’ – Compensation Completed
‘0’ – Compensation busy or not enabled
Done bit is asserted a few oscillator cycles before actual compensation interval compensation so that
back to back compensation can be enabled
Invalid Time bit. Indicates the time is invalid or changing and should not be read. This bit is asserted 1
oscillator clock cycle before and after the 1 Hz (seconds’) boundary. Not cleared on read. Write access
to time/date registers gets nullified (terminate normally) and no register value gets changed. Read during
INVAL bit asserted returns 16’hFFFF. No Transfer Error is asserted.
‘1’ – Counter values changing. Time/Date is invalid
‘0’ – Time can be read. Time is valid
Table 17-12. IRTC_STATUS Feild Descriptions
DD
is higher than V
lvwl-rising
(–2.41 V). When this bit is set, the IRTC registers are not
DD
is lower than V
Independent Robust Real Time Clock (IRTC)
lvwl-falling
(– 2.33 V), and automatically
17-19