MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 270

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Internal Clock Source (ICS)
11.4.3
The BDIV bits can be changed at anytime and the actual switch to the new frequency occurs immediately.
11.4.4
The low power bit (LP) is provided to allow the FLL to be disabled and thus conserve power when it is
not being used. The DRS bits can not be written while LP bit is 1.
However, in some applications it may be desirable to allow the FLL to be enabled and to lock for maximum
accuracy before switching to an FLL engaged mode. To do this, write the LP bit to 0.
11.4.5
The FLL has an option to change the clock multiplier for the selected DCO range such that it results in the
maximum bus frequency with a common 32.768 kHz crystal reference clock.
11.4.6
When IRCLKEN is set the internal reference clock signal is presented as ICSIRCLK, which can be used
as an additional clock source. To re-target the ICSIRCLK frequency, write a new value to the TRIM bits
in the ICSTRM register to trim the period of the internal reference clock:
The TRIM bits effect the ICSOUT frequency if the ICS is in FLL engaged internal (FEI), FLL bypassed
internal (FBI), or FLL bypassed internal low power (FBILP) mode.
Until ICSIRCLK is trimmed, programming low reference divider (RDIV) factors may result in ICSOUT
frequencies that exceed the maximum chip-level frequency and violate the chip-level clock timing
specifications (see the
If IREFSTEN is set and the IRCLKEN bit is written to 1, the internal reference clock keeps running during
stop mode in order to provide a fast recovery upon exiting stop.
All MCU devices are factory programmed with a trim value in a reserved memory location. This value is
uploaded to the ICSTRM register and ICS FTRIM register during any reset initialization. For finer
precision, trim the internal oscillator in the application and set the FTRIM bit accordingly.
11-16
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•
Writing a larger value slows down the ICSIRCLK frequency.
Writing a smaller value to the ICSTRM register speeds up the ICSIRCLK frequency.
Bus Frequency Divider
Low Power Bit Usage
DCO Maximum Frequency with 32.768 kHz Oscillator
Internal Reference Clock
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 1.11
Device Overview
chapter).
Freescale Semiconductor