MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 467

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.4.3
ADCCFG2 selects differential mode, the special high speed configuration for very high speed
conversions, and selects the long sample time duration during long sample mode.
Freescale Semiconductor
ADACKEN
ADLSTS
ADHSC
Field
1:0
3
2
Reset:
W
R
Configuration Register 2 (ADCCFG2)
Asynchronous clock output enable - ADACKEN enables the ADC’s asynchronous clock source and the clock
source output regardless of the conversion and input clock select (ADICLK bits) status of the ADC. Based on
MCU configuration the asynchronous clock may be used by other modules (see module introduction section).
Setting this bit allows the clock to be used even while the ADC is idle or operating from a different clock source.
Also, latency of initiating a single or first-continuous conversion with the asynchronous clock selected is reduced
since the ADACK clock is already operational.
0 Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a
1 Asynchronous clock and clock output enabled regardless of the state of the ADC
High Speed Configuration- ADHSC configures the ADC for very high speed operation. The conversion
sequence is altered (4 ADCK cycles added to the conversion time) to allow higher speed conversion
clocks.
0 Normal conversion sequence selected
1 High speed conversion sequence selected (4 additional ADCK cycles to total conversion time)
Long Sample Time Select - ADLSTS selects between the extended sample times when long sample time is
selected (ADLSMP=1). This allows higher impedance inputs to be accurately sampled or to maximize conversion
speed for lower impedance inputs. Longer sample times can also be used to lower overall power consumption
when continuous conversions are enabled if high conversion rates are not required.
00 Default longest sample time (20 extra ADCK cycles; 24 ADCK cycles total)
01 12 extra ADCK cycles; 16 ADCK cycles total sample time
10 6 extra ADCK cycles; 10 ADCK cycles total sample time
11 2 extra ADCK cycles; 6 ADCK cycles total sample time
conversion is active
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
7
0
0
Table 21-9. ADCCFG2 Register Field Descriptions
Figure 21-4. Configuration Register 2(ADCCFG2)
0
0
6
ADICLK
00
01
10
11
Table 21-8. Input Clock Select
0
0
5
Asynchronous clock (ADACK)
Alternate clock (ALTCLK)
Selected Clock Source
Bus clock divided by 2
0
0
4
Description
Bus clock
ADACKEN
0
3
ADHSC
Analog-to-Digital Converter (S08ADC16)
0
2
0
1
ADLSTS
0
0
21-11