MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 85

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.4.1
Features of the flash memory include:
3.4.2
The MCF51EM256 and MCF51EM128 devices each separate available flash into two distinct blocks.
Each block is controlled by its own, independent, flash controller. Memory mapping of the individual
arrays is impacted by the current state of IRTC_CFG_DATA[CFG0] as shown in
power-up, IRTC_CFG_DATA[CFG0] = 0, and Array 1 is located at the bottom of the map with Array 2
above it. Setting IRTC_CFG_DATA[CFG0] = 1 reverses the locations of the two arrays in the memory
map. The V1 ColdFire core will normally boot from 0x(00)00_0000. The procedure to swap flash arrays
must be located in RAM, and must include the following steps:
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The MCF51EM256 series incorporate dual flash controllers, allowing the microcontroller to
execute code from one flash array while programming the other.
Flash size
— MCF51EM256: Two flash arrays. Each is 131,072 bytes (128 sectors of 1024 bytes each)
— MCF51EM128: Two flash arrays. Each is 65,536 bytes (64 sectors of 1024 bytes each)
Automated program and erase algorithm
Fast program and sector erase operation
Burst program command for faster flash array program times
Single power supply program and erase
Command interface for fast program and erase operation
Up to 100,000 program/erase cycles at typical voltage and temperature
Flexible block protection (on any 2 KB memory boundary for each flash block)
Security feature to prevent unauthorized access to on-chip memory and resources
Auto power-down for low-frequency read accesses
Disable flash speculation by the V1 ColdFire CPU by setting CPUCR[FSD] to 1
Disable all interrupts
Toggle IRTC_CFG_DATA[CFG0]
Re-enable interrupts
If desired, re-enable flash speculation by the V1 ColdFire CPU by re-setting CPUCR[FSD] to 0
Jump back (using an indirect jump) to main application code residing in the flash memory
Features
Dual Flash Controllers
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
0x08 – 0x0B
0x08 – 0x0B
0x0C – 0x0F
0x0C – 0x0F
Addresses
Table 3-5. Alternate Bytes Setting (continued)
0x9ABC_DEF0
Desired Value
0x1234_5678
Values Programmed
0x9AFF_DEFF
0xFFBC_FFF0
0x12FF_56FF
0xFF34_FF78
Table
3-6. Upon initial
Memory
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