MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 457

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 21
Analog-to-Digital Converter (ADC16)
21.1
The 16-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation
within an integrated microcontroller system-on-chip.
21.1.1
The bus clock to each ADC can be gated on and off using the SCGC1_ADCx bits (see
“System Clock Gating Control 1 Register
bus clock to this module. To conserve power, the SCGC1_ADCx can be cleared to disable the clock to this
module when not in use. See
21.1.2
The hardware triggers of ADC1, ADC2, ADC3 and ADC4 are provided from PDB channel 1, 2, 3 and 4
correspondingly, when ADTRG is set in ADCxSC2.
When enabled, ADCx will be triggered every time PDB channel x TriggerA output is asserted. The PDB
channel x PreTriggerA and PreTriggerB will set the ADHWTSA and ADHWTSB correspondingly.
For details on ADC hardware trigger function, refer to
Selects”. For details on PDB, refer
Freescale Semiconductor
Introduction
ADC Clock Gating
Hardware Trigger
The registers APCTL1, APCTL2, APCTL3 and APCTL4 have no
functionality in the MCF51EM256 series. The pin control function is
performed by the Mux control, please refer to
Controls” for further information.
V
Ignore any references to stop1 low-power mode in this chapter, because this
device does not support it.
For details on low-power mode operation, refer to
“Modes of
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
BG
is from the MCU voltage regulator and V
Operation”.
Section 7.6, “Peripheral Clock Gating,”
Chapter 22, “Programmable Delay Block
(SCGC1)”). These bits are set after any reset, which enables the
NOTE
Section 21.5.4, “Hardware Trigger and Channel
Section 4.7, “Pin Mux
alt
is from V
Table 6-4
for details.
REF
in
(PDB).”
module.
Chapter 6,
Section 7.7.9,
21-1