MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 54

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Pins and Connections
2.2.4
The RESET pin defaults to hardware reset upon a power-on-reset event. During stop2, the RESET pin can
be used to wake the device from that state. There is a direct analog connection from this pad to the power
management controller wakeup pin.
The internal pullup on this pin is enabled upon any device reset.
RESET is normally connected to the standard 6-pin background debug connector, so a development
system can directly reset the MCU system. If desired, a manual external reset can be added by supplying
a simple switch to ground (pull reset pin low to force a reset).
In EMC-sensitive applications, an external RC filter is recommended on this pin. See
example.
2.2.5
The IRQ pin function acts as a non-maskable interrupt to the V1 ColdFire core. This pin can be
reprogrammed to function as PTA0.
2.2.6
During a power-on-reset (POR) or background debug force reset (see bit ENBDM in
“Extended Configuration/Status Register (XCSR),”
as a mode select pin. Immediately after any reset, the pin functions as the background pin and can be used
for background debug communication. The internal pullup on this pin is enabled upon any device reset.
If the BKGD/MS pin is unconnected, the microcontroller will enter normal operating mode at the rising
edge of the internal reset after a POR or forced BDC reset. If a debug system is connected to the 6-pin
standard background debug header, it can hold BKGD/MS low during a POR or immediately after issuing
a background debug force reset
The BKGD/MS pin is used primarily for background debug controller (BDC) communications using a
custom protocol that uses 16 clock cycles of the target microcontroller’s BDC clock per bit time. The target
microcontroller’s BDC clock could be as fast as the bus clock rate, so there must never be any significant
capacitance connected to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD/MS pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speed-up pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD/MS pin.
The BKGD/MS select pin can be reprogrammed to operate as PTC2 on this device. It must only be
programmed for use as an output, as an external signal driving this pin during startup may cause the device
to boot into debug mode.
1. Specifically, BKGD must be held low through the first 16 cycles after deassertion of the internal reset.
2-22
RESET Pin
IRQ
Background / Mode Select (BKGD/MS)
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
1
, which forces the microcontroller to halt mode.
for more information), the BKGD/MS pin functions
Freescale Semiconductor
Section 26.3.2,
Figure 2-3
for an