MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 543

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.4.2
For a segment on the LCD panel to be displayed, data must be written to the LCDWF registers. For LCD
pins enabled as frontplanes, each bit in the LCDWF registers corresponds to a segment on an LCD panel.
The different phases A-H represent the different backplanes of the LCD panel. The selected LCD duty
cycle controls the number of implemented phases. Refer to
phases follow the sequence shown.
For LCD pins enabled as a backplane, the LCDWF assigns the phase in which the backplane pin is active.
This is how backplane assignment is done.
An example of normal operation follows: enable LCD pin 0 to operate as backplane 0. Enable the LCD
pin 0 by setting PEN0 bit in the LCDPEN0 register. Configure LCD pin 0 as a backplane pin by setting
the BPEN0 bit in the LCDBPEN0 register. Finally, the BPALCD0 bit in the LCDWF0 is set to associate
LCD pin 0 with backplane phase A.This will configure LCD0 to operate as a backplane that is active in
Phase A.
For LCD pins enabled as a frontplane, writing a 1 to a given LCDWF location results in the corresponding
display segment being driven with the differential root mean square (RMS) voltage necessary to turn the
segment on during the phase selected. Writing a 0 to a given location results in the corresponding display
segment being driven with the differential RMS voltage necessary to turn the segment off during the phase
selected.
24.4.3
The LCD module can be configured to implement several different display modes. The bits ALT and
BLANK in the LCD-blink-control register (LCDBCTL) configure the different display modes. In normal
display mode (default), LCD segments are controlled by the data placed in the LCDWF registers, as
described in
and the frontplane and backplane pins are configured to clear all segments.
For alternate-display mode, the backplane sequence is modified for duty cycles of 1/4, 1/3, 1/2, and 1/1.
For four backplanes or less, the backplane sequence is modified as shown below. The altered sequence
allows two complete displays to be placed in the LDCDWF registers. The first display is placed in phases
A-D and the second in phases E-H in the case of four backplanes. If the LCD duty cycle is five backplanes
or greater, the ALT bit is ignored and creates a blank display. Refer to
information.
Using the alternate display function an inverse display can be accomplished for x4 mode and less by
placing inverse data in the alternate phases of the LCDWF registers.
Freescale Semiconductor
LCDWF Registers
LCD Display Modes
Section 24.4.2, “LCDWF
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Duty
1/1
1/2
Table 24-18. Alternate Display Backplane Sequence
Backplane Sequence
Registers.” For blank-display mode, the LCDWF data is bypassed
A B
A
Table 24-14
Alt. Backplane Sequence
E F
Table 24-19
E
for normal LCD operation the
for additional
LCD Driver Module
24-27