MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 154

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Modes of Operation
6.3
The ColdFire CPU has two primary user modes of operation, run and stop. (The CPU also supports a halt
mode that is used strictly for debug operations.) The STOP instruction is used to invoke stop and wait
modes for this family of devices.
The Systems Option Register 1 (SOPT1) contains two bits which control operation of the STOP
instruction. If SOPT1[WAITE] is set when STOP is executed, the wait mode is entered. Otherwise, if
SOPT1[STOPE] is set, the CPU enters one of the stop modes. It is illegal to execute a STOP instruction if
neither STOPE or WAITE are set. This results in reset assertion if the Instruction-related Reset Disable bit
in the CPU Control Register (CPUCR[IRD]) is cleared or an illegal instruction exception if CPUCR[IRD]
is set.
The MCF51EM256 series devices augment stop, wait, and run in a number of ways. The power
management controller (PMC) can run the device in fully-regulated mode, standby mode, and partial
power-down mode. Standby (loose regulation) or partial power-down can be programmed to occur
naturally as a result of a STOP instruction. Additionally, standby mode can be explicitly invoked via the
LPR (low-power) bit in the PMC System Power Management Status & Control Register 2
(SPMSC2[LPR]). Use of standby is limited to bus frequencies less than 125 kHz; and neither standby nor
partial power-down are allowed when XCSR[ENBDM] bit is set to enable debugging in stop and wait
modes.
During partial power-down mode, the regulator is in standby mode and much of the digital logic on the
chip is switched off. These interactions can be seen schematically in
conceptual purposes only. It does not reflect any sequence or time dependencies between the PMC and
other parts of the device, nor does it represent any actual design partitioning.
It is illegal for the software to have SPMSC2[PPDC] and SPMSC2[LPR] asserted concurrently. This
restriction arises because the sequence of events from normal to low-power modes involves use of both
bits. After entering a low-power mode, it is not possible to switch to another low-power mode.
6-2
SPMSC1[LVDSE]
SPMSC1[LVDE]
Overview
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
XCSR[ENBDM]
Figure 6-1. MCF51EM256 Series Power Modes — Conceptual Drawing
SOPT1[WAITE]
SOPT1[STOPE]
STOP
LVD Off
SPMSC2[LPR]
In Stop Mode
SPMSC2[PPDC]
Standby Enable
Figure
6-1. This figure is for
Partial Power Down
Standby
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