MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 602

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Version 1 ColdFire Debug (CF1_DEBUG)
26.4.1.5.1
The SYNC command is unlike other BDC commands because the host does not necessarily know the
correct speed to use for serial communications until after it has analyzed the response to the SYNC
command.
To issue a SYNC command, the host:
Upon detecting the sync request from the host (which is a much longer low time than would ever occur
during normal BDC communications), the target:
26-38
1
2
3
SYNC_PC
WRITE_CREG
WRITE_DREG
WRITE_MEM.sz
WRITE_MEM.sz_WS
WRITE_Rn
WRITE_XCSR_BYTE
WRITE_CSR2_BYTE
WRITE_CSR3_BYTE
This column identifies if the command generates an ACK pulse if operating with acknowledge mode enabled. See
Section 26.4.1.5.3, “ACK_ENABLE,”
The SYNC command is a special operation which does not have a command code.
If a GO command is received while the processor is not halted, it performs no operation.
1. Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (bus clock or
2. Drives BKGD high for a brief speed-up pulse to get a fast rise time. (This speedup pulse is typically
3. Removes all drive to the BKGD pin so it reverts to high impedance.
4. Listens to the BKGD pin for the sync response pulse.
1. Waits for BKGD to return to a logic high.
Command
Mnemonic
device-specific alternate clock source).
one cycle of the host clock which is as fast as the maximum target BDC clock.)
SYNC
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Classification
Non-Intrusive
Non-Intrusive
Non-Intrusive
Non-Intrusive
Background
Background
Command
Available
Available
Available
Always
Always
Always
Active
Active
Table 26-25. BDM Command Summary (continued)
for addition information.
if Enb?
ACK
Yes
Yes
Yes
Yes
Yes
No
No
No
No
1
(0x11+4 x sz)/ad24/wd.sz/d/ss Write the appropriately-sized (sz) memory
(0x10+4 x sz)/ad24/wd.sz/d
(0xC0+CRN)/wd32/d
(0x80+CRN)/wd32/d
(0x40+CRN)/wd32/d
Command
Structure
0x0D/wd8
0x0E/wd8
0x0F/wd8
0x01/d
Display the CPU’s current PC and capture
it in the PST trace buffer
Write one of the CPU’s control registers
Write one of the debug module’s control
registers
Write the appropriately-sized (sz) memory
value to the location specified by the 24-bit
address
value to the location specified by the 24-bit
address and report status
Write the requested general-purpose
register (An, Dn) of the CPU
Write the most significant byte of the debug
module’s XCSR
Write the most significant byte of the debug
module’s CSR2
Write the most significant byte of the debug
module’s CSR3
Description
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