MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 571

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The ColdFire debug architecture supports a number of hardware breakpoint registers that can be
configured into single- or double-level triggers based on the PC or operand address ranges with an optional
inclusion of specific data values. The triggers can be configured to halt the processor or generate a debug
interrupt exception. Additionally, these same breakpoint registers can be used to specify start/stop
conditions for recording in the PST trace buffer.
The core includes four PC breakpoint triggers and a set of operand address breakpoint triggers with two
independent address registers (to allow specification of a range) and an optional data breakpoint with
masking capabilities. Core breakpoint triggers are accessible through the serial BDM interface or written
through the supervisor programming model using the WDEBUG instruction.
26.3.1
CSR defines the debug configuration for the processor and memory subsystem and contains status
information from the breakpoint logic. CSR is accessible from the programming model using the
WDEBUG instruction and through the BDM port using the READ_DREG and WRITE_DREG
commands.
Freescale Semiconductor
1
2
3
The most significant bytes of the XCSR, CSR2, and CSR3 registers support special control functions and are writeable via
BDM using the WRITE_XCSR_BYTE, WRITE_CSR2_BYTE, and WRITE_CSR3_BYTE commands. They can be read from
BDM using the READ_XCSR_BYTE, READ_CSR2_BYTE, and READ_CSR3_BYTE commands. These 3 registers, along
with the CSR, can also be referenced as 32-bit quantities using the BDM READ_DREG and WRITE_DREG commands, but
the WRITE_DREG command only writes bits 23–0 of these three registers.
Each debug register is accessed as a 32-bit value; undefined fields are reserved and must be cleared.
The contents of the PST trace buffer is only read from BDM (32 bits per access) using READ_PSTB commands.
0x1A
0x1B
0x18
DRc
—
PC breakpoint register 1 (PBR1)
PC breakpoint register 2 (PBR2)
PC breakpoint register 3 (PBR3)
PST Trace Buffer n (PSTBn); n = 0–11 (0xB)
Configuration/Status Register (CSR)
Debug control registers can be written by the external development system
or the CPU through the WDEBUG instruction. These control registers are
write-only from the programming model and they can be written through the
BDM port using the WRITE_DREG command. In addition, the four
configuration/status registers (CSR, XCSR, CSR2, CSR3) can be read
through the BDM port using the READ_DREG command.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Register Name
Table 26-4. Debug Module Memory Map (continued)
NOTE
Width
(bits)
32
32
32
32
R (BDM)
Access
W
W
W
3
Version 1 ColdFire Debug (CF1_DEBUG)
Reset Value
PBR1[0] = 0
PBR2[0] = 0
PBR3[0] = 0
Undefined,
Unaffected
26.4.1.5.12/26-46
26.3.8/26-22
26.3.8/26-22
26.3.8/26-22
Section/
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