MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 375

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

In input capture mode, reading either byte (TPMCnVH or TPMCnVL) latches the contents of both bytes
into a buffer where they remain latched until the other half is read. This latching mechanism also resets
(becomes unlatched) when the TPMCnSC register is written (whether BDM mode is active or not). Any
write to the channel registers will be ignored during the input capture mode.
When BDM is active, the coherency mechanism is frozen such that the buffer latches remain in the state
they were in when the BDM became active, even if one or both halves of the channel register are read while
BDM is active. This assures that if the user was in the middle of reading a 16-bit register when BDM
became active, it will read the appropriate value from the other half of the 16-bit value after returning to
normal execution. The value read from the TPMCnVH and TPMCnVL registers in BDM mode is the value
of these registers and not the value of their read buffer.
In output compare or PWM modes, writing to either byte (TPMCnVH or TPMCnVL) latches the value
into a buffer. After both bytes are written, they are transferred as a coherent 16-bit value into the
timer-channel registers according to the value of CLKS bits and the selected mode, so:
The latching mechanism may be manually reset by writing to the TPMCnSC register (whether BDM mode
is active or not). This latching mechanism allows coherent 16-bit writes in either big-endian or little-endian
order which is friendly to various compiler implementations.
When BDM is active, the coherency mechanism is frozen such that the buffer latches remain in the state
they were in when the BDM became active even if one or both halves of the channel register are written
while BDM is active. Any write to the channel registers bypasses the buffer latches and directly write to
the channel register while BDM is active. The values written to the channel register while BDM is active
are used for PWM & output compare operation once normal execution resumes. Writes to the channel
Freescale Semiconductor
Reset
Reset
•
•
•
W
W
R
R
If (CLKS[1:0] = 00), then the registers are updated when the second byte is written.
If (CLKS[1:0] not = 00 and in output compare mode) then the registers are updated after the second
byte is written and on the next change of the TPM counter (end of the prescaler counting).
If (CLKS[1:0] not = 00 and in EPWM or CPWM modes), then the registers are updated after the
both bytes were written, and the TPM counter changes from (TPMMODH:TPMMODL - 1) to
(TPMMODH:TPMMODL). If the TPM counter is a free-running counter then the update is made
when the TPM counter changes from 0xFFFE to 0xFFFF.
Bit 15
Bit 7
0
0
7
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 16-12. TPM Channel Value Register High (TPMCnVH)
Figure 16-13. TPM Channel Value Register Low (TPMCnVL)
14
0
6
0
6
6
13
5
0
5
5
0
12
0
4
0
4
4
11
0
3
0
3
3
10
0
2
0
2
2
Timer/PWM Module(TPM)
1
9
0
1
1
0
Bit 8
Bit 0
0
0
0
0
16-13