MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 200

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ColdFire Core
8.2.8
The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control
bits. In supervisor mode, software can access the entire SR. In user mode, only the lower 8 bits (CCR) are
accessible. The control bits indicate the following states for the processor: trace mode (T bit), supervisor
or user mode (S bit), and master or interrupt state (M bit). All defined bits in the SR have read/write access
when in supervisor mode. The lower byte of the SR (the CCR) must be loaded explicitly after reset and
before any compare (CMP), Bcc, or Scc instructions execute.
8-8
CBRR
Field
BWD
23–0
ARD
FSD
IRD
IME
IAE
31
30
29
28
27
26
25
24
Address-related reset disable. Used to disable the generation of a reset event in response to a processor exception
caused by an address error, a bus error, an RTE format error, or a fault-on-fault halt condition.
0 The detection of these types of exception conditions or the fault-on-fault halt condition generate a reset event.
1 No reset is generated in response to these exception conditions.
Instruction-related reset disable. Used to disable the generation of a reset event in response to a processor exception
caused by the attempted execution of an illegal instruction (except for the ILLEGAL opcode), illegal line A, illegal
line F instructions, or a privilege violation.
0 The detection of these types of exception conditions generate a reset event.
1 No reset is generated in response to these exception conditions.
Interrupt acknowledge (IACK) enable. Forces the processor to generate an IACK read cycle from the interrupt
controller during exception processing to retrieve the vector number of the interrupt request being acknowledged. The
processor’s execution time for an interrupt exception is slightly improved when this bit is cleared.
0 The processor uses the vector number provided by the interrupt controller at the time the request is signaled.
1 IACK read cycle from the interrupt controller is generated.
Interrupt mask enable. Forces the processor to raise the interrupt level mask (SR[I]) to 7 during every interrupt
exception.
0 As part of an interrupt exception, the processor sets SR[I] to the level of the interrupt being serviced.
1 As part of an interrupt exception, the processor sets SR[I] to 7. This disables all level 1-6 interrupt requests but
Buffered write disable. The ColdFire core is capable of marking processor memory writes as bufferable or
non-bufferable.
0 Writes are buffered and the bus cycle is terminated immediately with zero wait states.
1 Disable the buffering of writes. In this configuration, the write transfer is terminated based on the response time
Note: If buffered writes are enabled (BWD = 0), any error status is lost as the immediate termination of the data
Reserved, must be cleared.
Flash speculation disabled. Disables certain performance-enhancing features related to address speculation in the
flash memory controller.
0 The flash controller tries to speculate on read accesses to improve processor performance by minimizing the
exposed flash memory access time. Recall the basic flash access time is two processor cycles.
1 Certain flash address speculation is disabled.
Crossbar round-robin arbitration enable. Configures the crossbar slave ports to fixed-priority or round-robin
arbitration.
0 Fixed-priority arbitration
1 Round robin arbitration
Reserved, must be cleared.
allows recognition of the edge-sensitive level 7 requests.
of the addressed destination memory device.
Status Register (SR)
transfer assumes an error-free completion.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table 8-3. CPUCR Field Descriptions
Description
Freescale Semiconductor