MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 603

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for
subsequent BDC communications. Typically, the host can determine the correct communication speed
within a few percent of the actual target speed and the serial protocol can easily tolerate this speed error.
26.4.1.5.2
Disables the serial communication handshake protocol. The subsequent commands, issued after the
ACK_DISABLE command, do not execute the hardware handshake protocol. This command is not
followed by an ACK pulse.
26.4.1.5.3
Enables the hardware handshake protocol in the serial communication. The hardware handshake is
implemented by an acknowledge (ACK) pulse issued by the target MCU in response to a host command.
The ACK_ENABLE command is interpreted and executed in the BDC logic without the need to interface
with the CPU. However, an acknowledge (ACK) pulse is issued by the target device after this command
is executed. This feature can be used by the host to evaluate if the target supports the hardware handshake
protocol. If the target supports the hardware handshake protocol, subsequent commands are enabled to
execute the hardware handshake protocol, otherwise this command is ignored by the target.
For additional information about the hardware handshake protocol, refer to
Interface Hardware Handshake Protocol,”
Freescale Semiconductor
2. Delays 16 cycles to allow the host to stop driving the high speed-up pulse.
3. Drives BKGD low for 128 BDC clock cycles.
4. Drives a 1-cycle high speed-up pulse to force a fast rise time on BKGD.
5. Removes all drive to the BKGD pin so it reverts to high impedance.
Disable host/target handshake protocol
Enable host/target handshake protocol
ACK_DISABLE
ACK_ENABLE
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
host →
host →
target
target
0x03
0x02
D
D
L
Y
L
Y
and
Section 26.4.1.7, “Hardware Handshake Abort Procedure.”
Version 1 ColdFire Debug (CF1_DEBUG)
Section 26.4.1.6, “Serial
Always Available
Always Available
26-39