MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 562

IC MCU 32BIT 256KB FLASH 100LQFP

MCF51EM256CLL

Manufacturer Part Number
MCF51EM256CLL
Description
IC MCU 32BIT 256KB FLASH 100LQFP
Manufacturer
Freescale Semiconductor
Series
MCF51EMr
Datasheets

Specifications of MCF51EM256CLL

Core Processor
Coldfire V1
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SCI, SPI
Peripherals
LCD, LVD, PWM, WDT
Number Of I /o
63
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
MCF51EM
Core
ColdFire V1
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
RS-232, LIN
Maximum Clock Frequency
50 MHz
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
DEMOEM
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF51EM256CLL
Manufacturer:
FREESCALE
Quantity:
110
Part Number:
MCF51EM256CLL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Programmable Reference Analog Comparator (PRACMP)
The programmable reference generator (PRG) includes a 32-level DAC (digital to analog convertor) and
relevant control logic. PRG can select one of two reference inputs, V
regulated Vdd), as the DAC input V
it converts the data set in PRGOS[4:0] bits of PRACMPxC1 to a stepped analog output which is fed into
ACMP as an internal reference input. This stepped analog ouput is also mapped out of the module. The
output voltage range is from V
The ACMP can achieve the analog comparison between positive input and negative input, and then give
out a digital output and relevant interrupt. Both the positive and negative input of ACMP can be selected
from the eight common inputs: seven external reference inputs and one internal reference input from the
PRG output. The positive input of ACMP is selected by ACPSEL[2:0] bits of PRACMPxC0 and the
negative input is selected by ACNSEL[2:0] bits of PRACMPxC0. Any pair of the eight inputs can be
compared by configuring the PRACMPxC0 with the appropriate value.
After the ACMP is enabled by setting ACEN in PRACMPxCS, the comparison result appears as a digital
output. Whenever a valid edge defined in ACINTS[1:0] occurs, the ACMPF bit in PRACMPxCS register
is asserted. If ACIEN is set, a PRACMP CPU interrupt occurs. The valid edge is defined by
ACINTS[1:0].When ACINTS[1:0] = 00, both the rising edge and falling edge on the ACMP output are
valid. When ACINTS[1:0] = 01, only the falling edge on ACMP output is valid. When ACINTS[1:0] =
10, only rising edge on ACMP output is valid. ACINTS[1:0] = 11 is reserved.
The ACMP output is synchronized by the bus clock to generate ACMPO bit in PRACMPxCS so that the
CPU can read the comparison. In stop3 mode if the output of ACMP is changed, ACMPO can’t be updated
in time. The output can be synchronized and the ACMPO bit can be updated upon the waking up of the
CPU because of the availability of the bus clock. The ACMPO changes following the comparison result,
so it can serve as a tracking flag that continuously indicates the voltage delta on the inputs.
If a reference input external to the chip is selected as an input of ACMP, the corresponding ACIPE bit of
PRACMPxC2 should be set to enable the input from pad interface. If the output of the ACMP needs to be
put onto the external pin, the ACOPE bit of PRACMPxCS must be set to enable the ACMP pin function
of pad logic.
25.5
The two parts of PRACMP (PRG and ACMP) can be set up and operated independently. But if the PRG
works as an input of the ACMP, the PRG must be configured before the ACMP is enabled.
Because the input-switching can cause problems on the ACMP inputs, the user should complete the input
selection before enableing the ACMP and should not change the input selection setting when the ACMP
is enabled to avoid unexpected output. Similarly, because the programmable reference generator (PRG)
experiences a setup delay after the PRGOS[4:0] is changed, the user should complete the setting of
PRGOS[4:0] before PRG is enabled.
25.6
During a reset the PRACMP is configured in the default mode. Both ACMP and PRG are disabled.
25-8
Setup and Operation of PRACMP
Resets
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
in
/32 to V
in
by setting PRGINS bit of PRACMPxC1. After the DAC is enabled,
in.
.The step size is V
in
/32.
in1
(external Vdd) or V
Freescale Semiconductor
in2
(internal

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