MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 372

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timer/PWM Module(TPM)
When BDM is active, the timer counter is frozen (this is the value that will be read by user); the coherency
mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became
active, even if one or both counter halves are read while BDM is active. This assures that if the user was
in the middle of reading a 16-bit register when BDM became active, it will read the appropriate value from
the other half of the 16-bit value after returning to normal execution.
16.3.3
The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM
counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock, and
the overflow flag (TOF) becomes set. Writing to TPMMODH or TPMMODL inhibits the TOF bit and
overflow interrupts until the other byte is written. Reset sets the TPM counter modulo registers to 0x0000
which results in a free running timer counter (modulo disabled).
Writing to either byte (TPMMODH or TPMMODL) latches the value into a buffer and the registers are
updated with the value of their write buffer according to the value of CLKS bits, so:
The latching mechanism may be manually reset by writing to the TPMSC address (whether BDM is active
or not).
When BDM is active, the coherency mechanism is frozen such that the buffer latches remain in the state
they were in when the BDM became active, even if one or both halves of the modulo register are written
while BDM is active. Any write to the modulo registers bypasses the buffer latches and directly writes to
the modulo register while BDM is active.
16-10
Reset
Reset
•
•
W
W
R
R
If (CLKS[1:0] = 00), then the registers are updated when the second byte is written
If (CLKS[1:0] not = 00), then the registers are updated after both bytes were written, and the TPM
counter changes from (TPMMODH:TPMMODL - 1) to (TPMMODH:TPMMODL). If the TPM
counter is a free-running counter, the update is made when the TPM counter changes from 0xFFFE
to 0xFFFF
Bit 15
Bit 7
TPM Counter Modulo Registers (TPMMODH:TPMMODL)
0
0
7
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 16-9. TPM Counter Modulo Register High (TPMMODH)
14
6
0
0
6
6
Figure 16-8. TPM Counter Register Low (TPMCNTL)
Any write to TPMCNTL clears the 16-bit counter
13
5
5
0
5
0
12
4
0
0
4
4
11
3
0
0
3
3
10
2
0
0
2
2
Freescale Semiconductor
1
1
0
1
9
0
Bit 0
Bit 8
0
0
0
0