MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 401

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

This is the control register and governs all operations being done inside the IRTC. This register is used to
specify the software reset, compensation controls, tamper controls and write protection control. Details of
compensation and tamper logic are given in the
There is no enable bit for the IRTC as this block is functional after reset and cannot be disabled. In Basic
& Standard Feature sets, only Bits 15 & 8 are valid and other bits are reserved.
The write protect bits are the only bits that are freely writeable by CPU. Rest of all bits, registers and RAM
are protected via a write protect mechanism. The write protect bits WE[1:0] are self clearing bits that
always return zeros on read. The above mentioned sequence should be written into these bits to enable or
disable write protection.
Depending on the BCD format enable bit, the width of time (seconds, minutes and hours) and day related
registers changes and the values in the register becomes as follows:
The table below shows how data gets changed on reads. The reverse happens for writes. Data input is in
BCD and converted to binary before storing in appropriate registers.
Freescale Semiconductor
DSTEN
ALARM
MATCH
Field
5–4
3–2
1–0
WE
6
IRTC_HOURMIN
Register Name
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Daylight Saving Enable. Automatic adjustment of time is done when enabled.
‘1’ – Enabled. Daylight Saving changes are applied.
‘0’ – Disabled. Daylight Saving changes are NOT applied.
Reserved bits. Not writeable. Read returns zeros.
Alarm Match bits. These bits define which time and calendar counters will be used for matching and
generate an alarm
“00” – Only Seconds, Minutes and Hours matched
“01” – Only Seconds, Minutes, Hours and Days matched
“10” – Only Seconds, Minutes, Hours, Days and Months matched
“11” – Only Seconds, Minutes, Hours, Days, Months and Year (offset) matched
Write Enable bits. Controls the entry and exit into/from the Register/Memory write protection mode. Self
clearing bits. Reads will return zeros.
‘10’
‘00 – 01 – 11 – 10’ ◊ Disable Write Protection – Registers are unlocked
NOTE: When the registers are unlocked, they remain in this unlocked state for a time of 1 to 2 seconds
after which the registers are automatically locked. After power-on-reset too, the registers come out as
unlocked but they get locked automatically 14 to 15 seconds after power on.
Enable Write Protection – Registers are locked
Table 17-11. Register Changes for BCD Format
Table 17-10. IRTC_CTRL Field Descriptions
Bits 12:8 – Hour
Bits 5:0 – Minutes
Values stored in Binary
BCD Enable = ‘0’
Section 17.8, “Block Description (Brief
Description
Bits 15:8 – Hour
Bits 7:0 – Minutes
Independent Robust Real Time Clock (IRTC)
Values stored in BCD.
BCD Enable = ‘1’
Overview).”
17-17