MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 186

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
Resets, Interrupts, and General System Control
7.7.10
This register contains control bits to enable or disable the bus clock to the SPI, LCD, IRQ, VREF and
PRACMP modules. Gating off the clocks to unused peripherals is used to reduce the microcontroller’s run
and wait currents. See
7-20
This bit is reset to 1 on 100-pin package and 0 on 80-pin package.
Reset:
CMP2
CMP1
ADC2
ADC1
Field
Field
SCI3
SCI2
SCI1
IIC
5
4
3
2
1
0
7
6
W
R
CMP2
System Clock Gating Control 2 Register (SCGC2)
ADC 2 Clock Gate Control — This bit controls the clock gate to the ADC 2 module.
0 Bus clock to the ADC 2 module is disabled.
1 Bus clock to the ADC 2 module is enabled.
ADC 1 Clock Gate Control — This bit controls the clock gate to the ADC 1 module.
0 Bus clock to the ADC 1 module is disabled.
1 Bus clock to the ADC 1 module is enabled.
IIC2 Clock Gate Control — This bit controls the clock gate to the IIC2 module.
0 Bus clock to the IIC2 module is disabled.
1 Bus clock to the IIC2 module is enabled.
SCI3 Clock Gate Control — This bit controls the clock gate to the SCI3 module.
0 Bus clock to the SCI3 module is disabled.
1 Bus clock to the SCI3 module isenabled.
SCI2 Clock Gate Control — This bit controls the clock gate to the SCI2 module.
0 Bus clock to the SCI2 module is disabled.
1 Bus clock to the SCI2 module isenabled.
SCI1 Clock Gate Control — This bit controls the clock gate to the SCI1 module.
0 Bus clock to the SCI1 module is disabled.
1 Bus clock to the SCI1 module isenabled.
PRACMP2 Clock Gate Control — This bit controls the clock gate to the PRACMP2 module.
0 Bus clock to the PRACMP2 module is disabled.
1 Bus clock to the PRACMP2 module isenabled.
PRACMP1 Clock Gate Control — This bit controls the clock gate to the PRACMP1 module.
0 Bus clock to the PRACMP1 module is disabled.
1 Bus clock to the PRACMP1 module isenabled.
1
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 7-11. System Clock Gating Control 2 Register (SCGC2)
Section 7.6, “Peripheral Clock Gating,”
CMP1
1
6
Table 7-15. SCGC1 Bit Field Descriptions
Table 7-16. SCGC2 Bit Field Descriptions
VREF
1
5
IRQ
1
4
Description
Description
LCD
3
1
for more information.
SPI3
—
2
1
Freescale Semiconductor
SPI2
1
1
SPI1
1
0