MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 209

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

If the processor is not in trace mode and executes a stop instruction where the immediate operand sets
SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points
to the instruction after the stop, and the SR reflects the value loaded in step 2.
Because ColdFire processors do not support any hardware stacking of multiple exceptions, it is the
responsibility of the operating system to check for trace mode after processing other exception types. As
an example, consider a TRAP instruction execution while in trace mode. The processor initiates the trap
exception and then passes control to the corresponding handler. If the system requires that a trace exception
be processed, it is the responsibility of the trap exception handler to check for this condition (SR[T] in the
exception stack frame set) and pass control to the trace handler before returning from the original
exception.
8.3.3.6
The default operation of the V1 ColdFire processor is the generation of an illegal opcode reset event if an
unimplemented line-A opcode is detected. If CPUCR[IRD] is set, the reset is disabled and a processor
exception is generated as detailed below.
A line-A opcode is defined when bits 15-12 of the opword are 0b1010. This exception is generated by the
attempted execution of an undefined line-A opcode.
8.3.3.7
The default operation of the V1 ColdFire processor is the generation of an illegal opcode reset event if an
unimplemented line-F opcode is detected. If CPUCR[IRD] is set, the reset is disabled and a processor
exception is generated as detailed below.
A line-F opcode is defined when bits 15-12 of the opword are 0b1111. This exception is generated when
attempting to execute an undefined line-F opcode.
8.3.3.8
See
which is generated in response to a hardware breakpoint register trigger. The processor does not generate
an IACK cycle, but rather calculates the vector number internally (vector number 12). Additionally,
SR[M,I] are unaffected by the interrupt.
8.3.3.9
The default operation of the V1 ColdFire processor is the generation of an illegal address reset event if an
RTE format error is detected. If CPUCR[ARD] is set, the reset is disabled and a processor exception is
generated as detailed below.
When an RTE instruction is executed, the processor first examines the 4-bit format field to validate the
frame type. For a ColdFire core, any attempted RTE execution (where the format is not equal to {4,5,6,7})
generates a format error. The exception stack frame for the format error is created without disturbing the
original RTE frame and the stacked PC pointing to the RTE instruction.
Freescale Semiconductor
Chapter 26, “Version 1 ColdFire Debug (CF1_DEBUG),”
Unimplemented Line-A Opcode
Unimplemented Line-F Opcode
Debug Interrupt
RTE and Format Error Exception
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
for a detailed explanation of this exception,
ColdFire Core
8-17