MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 465

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.4.2
ADCCFG1 selects the mode of operation, clock source, clock divide, and configure for low power or long
sample time.
Freescale Semiconductor
ADCHn[4:0]
DIFFn
Field
4:0
5
Reset:
W
R
Configuration Register 1 (ADCCFG1)
Differential Mode Enable - DIFFn configures the ADC to operate in differential mode. When enabled this mode
automatically selects from the differential channels, changes the conversion algorithm and the number of cycles
to complete a conversion.
0 Single-ended conversions and input channels are selected
1 Differential conversions and input channels are selected
Input Channel Select - The ADCHn bits form a 5-bit field that selects one of the input channels. The input
channel decode is dependent upon the value of the DIFFn bit as detailed in
The successive approximation converter subsystem is turned off when the channel select bits are all set(ADCHn
= 11111). This feature allows for explicit disabling of the ADC and isolation of the input channel from all sources.
Terminating continuous conversions this way prevents an additional, single conversion from being performed. It
is not necessary to set the channel select bits to all ones to place the ADC in a low-power state when continuous
conversions are not enabled because the module automatically enters a low-power state when a conversion
completes.
1
2
ADLPC
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
00000–00011
00100-10111
11000-11001
DAD0-DAD3 are associated with the input pin pairs DADPx and DADMx.
Voltage Reference selected is determined by the REFSEL bits in the ADCSC2 register.
Refer to
7
0
ADCHn
11010
11011
11100
11101
11110
11111
Table 21-3. ADCSC1:ADCSC1n Field Descriptions (continued)
Section 21.5.3
0
Figure 21-3. Configuration Register (ADCCFG1)
6
Input Selected when DIFFn=0
ADIV
Temp Sensor (single-ended)
Bandgap (single-ended)
Table 21-4. Input Channel Select
for more information on voltage reference selection.
DADP0-DADP3
0
5
AD4-AD23
Reserved
Reserved
V
V
REFSH
REFSL
ADLSMP
2
2
0
4
Module disabled
Description
Input Selected when DIFFn=1
0
3
Temp Sensor (differential)
MODE
-V
Bandgap (differential)
REFSH
DAD0-DAD3
Reserved
Reserved
Reserved
Reserved
2
Analog-to-Digital Converter (S08ADC16)
0
2
(differential)
Table
1
21-4.
0
1
ADICLK
0
0
21-9