MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 342

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Inter-Integrated Circuit (IIC)
15.3.3
15-4
Reset
AD[7:1]
MULT
Field
Field
ICR
7:1
7:6
5:0
W
R
IIC Frequency Divider Register (IICF)
Slave Address 1— The AD[7:1] field contains the slave address to be used by the IIC module. This field is used
on the 7-bit address scheme and the lower seven bits of the 10-bit address scheme.
IIC Multiplier Factor — The MULT bits define the multiplier factor mul. This factor is used along with the SCL
divider to generate the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below.
00 mul = 01
01 mul = 02
10 mul = 04
11 Reserved
IIC Clock Rate — The ICR bits are used to prescale the bus clock for bit rate selection. These bits and the MULT
bits are used to determine the IIC baud rate, the SDA hold time, the SCL Start hold time and the SCL Stop hold
time.
The SCL divider multiplied by multiplier factor mul is used to generate IIC baud rate.
SDA hold time is the delay from the falling edge of SCL (IIC clock) to the changing of SDA (IIC data).
SCL Start hold time is the delay from the falling edge of SDA (IIC data) while SCL is high (Start condition) to the
falling edge of SCL (IIC clock).
SCL Stop hold time is the delay from the rising edge of SCL (IIC clock) to the rising edge of SDA
SDA (IIC data) while SCL is high (Stop condition).
0
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table 15-4
MULT
SCL Start hold time = bus period (s) * mul * SCL Start hold value
SCL Stop hold time = bus period (s) * mul * SCL Stop hold value
0
6
provides the SCL divider and hold values for corresponding values of the ICR.
SDA hold time = bus period (s) * mul * SDA hold value
Figure 15-3. IIC Frequency Divider Register (IICF)
IIC baud rate = bus speed (Hz)/(mul * SCL divider)
Table 15-2. IICA1 Field Descriptions
Table 15-3. IICF Field Descriptions
0
5
0
4
Description
Description
3
0
ICR
0
2
Freescale Semiconductor
0
1
Eqn. 15-1
Eqn. 15-2
Eqn. 15-3
Eqn. 15-4
0
0