MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 30

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Device Overview
1.3.4
In order to save power, peripheral clocks can be shut off by programming the system clock gating registers.
For details, refer to
1.3.5
The ICS operates in one of the modes described in
clarity’s sake. See the
1.3.6
Figure 1-4
transistions. See
1-12
FLL Engaged Internal (FEI)
FLL Engaged External (FEE)
FLL Bypassed Internal (FBI)
FLL Bypassed External (FBE)
FLL Bypassed Internal Low Power
(FBILP)
FLL Bypassed External Low
Power (FBELP)
STOP
shows the valid state transitions for the ICS. The arrows indicate the permitted mode
Clock Gating
ICS Modes of Operation
ICS Mode State Diagram
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Chapter 11, “Internal Clock Source
Mode
Section 7.6, “Peripheral Clock
Chapter 11, “Internal Clock Source
Default. ICSOUT is derived from the FLL clock, which is controlled by the
internal reference clock. The FLL clock frequency locks to a multiple of the
internal reference frequency. ICSLCLK is derived from the FLL.
ICSOUT is derived from the FLL clock, which is controlled by the external
reference clock. The external reference clock that is enabled can be
produced by an external crystal, ceramic resonator, or another external
clock source connected to the required crystal oscillator (XOSC).
ICSOUT is derived from the internal reference clock; the FLL is
operational, but its output clock is not used. This mode is useful to allow
the FLL to acquire its target frequency while the ICSOUT clock is driven
from the internal reference clock.
ICSOUT is derived from the external reference clock; the FLL is
operational, but its output clock is not used. This mode is useful to allow
the FLL to acquire its target frequency while ICSOUT is driven from the
external reference clock.
ICSOUT is derived from the internal reference clock.
The FLLs are disabled, and ICSLCLK is not available for BDC
communications. If the BDM becomes enabled, the mode switches to one
of the bypassed internal modes.
ICSOUT is derived from the external reference clock. The external
reference clock that is enabled can be produced by an external crystal,
ceramic resonator, or another external clock source connected to the
required crystal oscillator (XOSC).
The FLLs are disabled, and ICSLCLK is not available for BDC
communications. If the BDM becomes enabled, the mode switches to one
of the bypassed external mode.
Entered whenever the MCU enters a stop state. The FLL is disabled, and
all ICS clock signals are static except that ICSIRCLK can be active in stop
mode under certain conditions.
Table 1-7. ICS Clock Modes
Gating.”
Table
(ICS),” for additional details.
1-7. This information has been abbreviated for
(ICS),” for additional details.
Description
Freescale Semiconductor