MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 567

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

There are two fields in debug registers which provide revision information: the hardware revision level in
CSR and the 1-pin debug hardware revision level in CSR2.
revisions.
26.1.2
The Version 1 ColdFire debug definition supports the following features:
26.1.3
V1 ColdFire devices typically implement a number of modes of operation, including run, wait, and stop
modes. Additionally, the operation of the core’s debug module is highly dependent on a number of chip
configurations which determine its operating state.
When operating in secure mode, as defined by a 2-bit field in the flash memory examined at reset, BDM
access to debug resources is extremely restricted. It is possible to tell that the device has been secured, and
Freescale Semiconductor
•
•
•
•
•
•
Revision
CF1_B+
B+
concurrent operation of the processor and BDM-initiated memory commands. In addition, the
option is provided to allow interrupts to occur. See
Program trace support—The ability to determine the dynamic execution path through an
application is fundamental for debugging. The V1 solution implements a trace buffer that records
processor execution status and data, which can be subsequently accessed by the external emulator
system to provide program (and optional partial data) trace information. See
Support”.
A
B
Classic ColdFire DEBUG_B+ functionality mapped into the single-pin BDM interface
Real time debug support, with 6 hardware breakpoints (4 PC, 1 address pair and 1 data) that can be
configured into a 1- or 2-level trigger with a programmable response (processor halt or interrupt)
Capture of compressed processor status and debug data into on-chip trace buffer provides program
(and optional slave bus data) trace capabilities
On-chip trace buffer provides programmable start/stop recording conditions plus support for
obtrusive or PC-profiling modes
Debug resources are accessible via single-pin BDM interface or the privileged WDEBUG
instruction from the core
Features
Modes of Operations
CSR[HRL]
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
0000
0001
1001
1001
CSR2[D1HRL]
0001
N/A
N/A
N/A
Table 26-1. Debug Revision Summary
Initial ColdFire debug definition
BDM command execution does not affect hardware breakpoint logic
Added BDM address attribute register (BAAR)
BKPT configurable interrupt (CSR[BKD])
Level 1 and level 2 triggers on OR condition, in addition to AND
SYNC_PC command to display the processor’s current PC
Added 3 PC breakpoint registers PBR1–3
Converted to HCS08 1-pin BDM serial interface
Added PST compression and on-chip PST/DDATA buffer for program trace
Section 26.4.2, “Real-Time Debug
Table 26-1
Enhancements
summarizes the various debug
Version 1 ColdFire Debug (CF1_DEBUG)
Section 26.4.3, “Trace
Support”.
26-3