MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 294

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16-Bit Serial Peripheral Interface (SPI16)
13.3.3
This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or
written at any time.
13-8
MODFEN
BIDIROE
SPISWAI
Reset
SPC0
Field
4
3
1
0
W
R
SPI Baud Rate Register (SPIxBR)
Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or
effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to
Table 13-2
0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0) = 1,
BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin.
Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO
(SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 = 0, BIDIROE has no meaning or effect.
0 Output driver disabled so SPI data I/O pin acts as an input
1 SPI I/O pin enabled as an output
SPI Stop in Wait Mode — This bit is used for power conservation while in wait.
0 SPI clocks continue to operate in wait mode
1 SPI clocks stop when the MCU enters wait mode
SPI Pin Control 0 — This bit enables bidirectional pin configurations as shown in
0 SPI uses separate pins for data input and data output.
1 SPI configured for single-wire bidirectional operation.
0
0
7
Bidirectional
Bidirectional
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Pin Mode
Normal
Normal
= Unimplemented or Reserved
for details)
SPPR2
Table 13-3. SPIxC2 Register Field Descriptions (continued)
0
6
SPC0
Figure 13-5. SPI Baud Rate Register (SPIxBR)
Table 13-4. Bidirectional Pin Configurations
0
1
0
1
SPPR1
0
5
BIDIROE
Master Mode of Operation
Slave Mode of Operation
X
X
0
1
0
1
SPPR0
MISO not used by SPI
0
4
Description
Slave Out
Master In
Slave I/O
Slave In
MISO
SPR3
3
0
MOSI not used by SPI
SPR2
0
2
Master Out
Master I/O
Master In
SlaveIn
MOSI
Table
Freescale Semiconductor
SPR1
13-4.
0
1
SPR0
0
0