MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 589

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.3.10 Data Breakpoint and Mask Registers (DBR, DBMR)
DBR specifies data patterns used as part of the trigger into debug mode. DBR bits are masked by setting
corresponding DBMR bits, as defined in TDR.
DBR and DBMR are accessible in supervisor mode using the WDEBUG instruction and through the BDM
port using the WRITE_DREG commands.
The DBR supports aligned and misaligned references.
processor address, access size, and location within the 32-bit data bus.
Freescale Semiconductor
Address
Address
Field
Field
Field
Field
Mask
31–0
31–0
31–0
31–0
Data
DRc[4:0]: 0x0E (DBR)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Low address. Holds the 32-bit address marking the lower bound of the address breakpoint range. Breakpoints for
specific addresses are programmed into ABLR.
High address. Holds the 32-bit address marking the upper bound of the address breakpoint range.
Data breakpoint value. Contains the value to be compared with the data value from the processor’s local bus as a
breakpoint trigger.
Data breakpoint mask. The 32-bit mask for the data breakpoint trigger.
0 The corresponding DBR bit is compared to the appropriate bit of the processor’s local data bus
1 The corresponding DBR bit is ignored
W
R
0x0F (DBMR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 26-14. Data Breakpoint & Mask Registers (DBR, DBMR)
Table 26-21. DBMR Field Descriptions
Table 26-19. ABHR Field Description
Table 26-18. ABLR Field Description
Table 26-20. DBR Field Descriptions
Data (DBR); Mask (DBMR)
Description
Description
Description
Description
Table 26-22
shows the relationships between
Version 1 ColdFire Debug (CF1_DEBUG)
Access: Supervisor write-only
8
7
6
5
BDM write-only
4
3
2
1
0
26-25