R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 973

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Bit 5 — Sleep Mode (MCR5): Enables or disables Sleep mode transition. If this bit is set, while
RCAN-TL1 is in halt mode, the transition to sleep mode is enabled. Setting MCR5 is allowed after
entering Halt mode. The two Error Counters (REC, TEC) will remain the same during Sleep
mode. This mode will be exited in two ways:
1. by writing a ‘0’ to this bit position,
2. or, if MCR[7] is enabled, after detecting a dominant bit on the CAN bus.
If Auto wake up mode is disabled, RCAN-TL1 will ignore all CAN bus activities until the sleep
mode is terminated. When leaving this mode the RCAN-TL1 will synchronise to the CAN bus (by
checking for 11 recessive bits) before joining CAN Bus activity. This means that, when the No.2
method is used, RCAN-TL1 will miss the first message to receive. CAN transceivers stand-by
mode will also be unable to cope with the first message when exiting stand by mode, and the S/W
needs to be designed in this manner.
In sleep mode only the following registers can be accessed: MCR, GSR, IRR and IMR.
Important: RCAN-TL1 is required to be in Halt mode before requesting to enter in Sleep mode.
That allows the CPU to clear all pending interrupts before entering sleep mode. Once all interrupts
are cleared RCAN-TL1 must leave the Halt mode and enter Sleep mode simultaneously (by
writing MCR[5] = 1 and MCR[1] = 0 at the same time).
Bit 4 — Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Bit 3 — Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Bit 2 — Message Transmission Priority (MCR2): MCR2 selects the order of transmission for
pending transmit data. If this bit is set, pending transmit data are sent in order of the bit position in
the Transmission Pending Register (TXPR). The order of transmission starts from Mailbox-31 as
the highest priority, and then down to Mailbox-1 (if those mailboxes are configured for
transmission). Please note that this feature cannot be used for time trigger transmission of the
Mailboxes 24 to 30.
If MCR2 is cleared, all messages for transmission are queued with respect to their priority (by
running internal arbitration). The highest priority message has the Arbitration Field (STDID + IDE
bit + EXTID (if IDE = 1) + RTR bit) with the lowest digital value and is transmitted first. The
internal arbitration includes the RTR bit and the IDE bit (internal arbitration works in the same
Bit 5: MCR5
0
1
Description
RCAN-TL1 sleep mode released (Initial value)
Transition to RCAN-TL1 sleep mode enabled
Section 19 Controller Area Network (RCAN-TL1)
Rev. 3.00 Sep. 28, 2009 Page 941 of 1650
REJ09B0313-0300