R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1022

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 19 Controller Area Network (RCAN-TL1)
19.4.2
RCAN-TL1 is considered in configuration mode or after a H/W (Power On Reset)/S/W (MCR[0])
reset or when in Halt mode. In both conditions RCAN-TL1 cannot join the CAN Bus activity and
configuration changes have no impact on the traffic on the CAN Bus.
• After a Reset request
The following sequence must be implemented to configure the RCAN-TL1 after (S/W or H/W)
reset. After reset, all the registers are initialised, therefore, RCAN-TL1 needs to be configured
before joining the CAN bus activity. Please read the notes carefully.
Rev. 3.00 Sep. 28, 2009 Page 990 of 1650
REJ09B0313-0300
Configuration of RCAN-TL1
Notes:
1.
2.
3.
4.
RTR, IDE, MBC, MBIMR, DART,
(STD-ID, EXT-ID, LAFM, DLC,
RCAN-TL1 Timer Reg Setting
SW reset could be performed at any time by setting MCR[0] = 1.
Mailboxes are comprised of RAMs, therefore, please initialise all the mailboxes enabled by MBC.
If there is no TXPR set, RCAN-TL1 will receive the next incoming message. If there is a TXPR(s)
Timer can be started at any time after the Timer Control regs and Tx-Trigger Time are set.
set, RCAN-TL1 will start transmission of the message and will be arbitrated by the CAN bus.
If it loses the arbitration, it will become a receiver.
MCR[0] = 1 (automatically
Clear Required IMR Bits
IRR[0] = 1, GSR[3] = 1
Power On/SW Reset*
in hardware reset only)
ATX, NMC, Tx-Trigger
Time Message-Data)*
Set Bit Timing (BCR)
Configure MCR[15]
Clear IRR[0] Bit
(automatically)
Mailbox Setting
Clear MCR[0]
Figure 19.14 Reset Sequence
1
2
Configuration Mode
Reset Sequence
Receive*
Detect 11 recessive bits and
RCAN-TL1 is in Tx_Rx Mode
- Set TXPR to start transmission
- or stay idle to receive
3
Join the CAN bus activity
GSR[3] = 0?
Transmit*
Yes
Transmission_Reception
(Tx_Rx) Mode
3
Timer Start*
No
4