R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1244

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 23 USB 2.0 Host/Function Module (USB)
(b)
Figure 23.16 shows the timing at which, when using a pipe with a double buffer, the other buffer
can be accessed after reading from or writing to one buffer has been completed.
When using a double buffer, access to the FIFO port should be carried out after waiting 300 ns and
6 clock cycles at a peripheral clock after the access made just prior to toggling.
The same timing applies when a short packet is being sent based on the BVAL = 1 setting using
the IN direction pipe.
Rev. 3.00 Sep. 28, 2009 Page 1212 of 1650
REJ09B0313-0300
Figure 23.16 Timing at which the FRDY and DTLN Bits are Determined after Reading
Timing at which the FIFO Port can be Accessed after Reading/Writing has been
Completed when Using a Double Buffer
Figure 23.15 Timing at which the FRDY and DTLN Bits are Determined after
PMS_N
CURPIPE
FRDY
DTLN
PMS_N
CURPIPE
FRDY
DTLN
from or Writing to a Double Buffer has been Completed
Access just prior to buffer toggling
Writing of the CURPIPE bit
Buffer-A
Buffer-A
PIPE-A
PIPE-A
PIPE-A
min. bus clock × 1
min. 20 ns
Changing a Pipe
max. 50 ns +
bus clock × 3
Undefined
max. 300 ns +
bus clock × 6
Undefined
Undefined
PIPE-A
PIPE-B
max. 450 ns +
bus clock × 8
Buffer-B
Buffer-B
PIPE-B
PIPE-B