R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1457

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

(2)
Software standby mode is canceled by interrupts (NMI or IRQ) or a reset (manual reset or power-
on reset). In clock modes 0, 1 and 3, clock signal starts to be output from the CKIO pin.
• Canceling by an interrupt
• Canceling by a reset
When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit
(NMIE) in interrupt control register 0 (ICR0) of the interrupt controller (INTC)) or the falling
edge or rising edge of an IRQ pin (IRQ7 to IRQ0) (selected by the IRQn sense select bits
(IRQn1S and IRQn0S) in interrupt control register 1 (ICR1) of the interrupt controller (INTC))
is detected, clock oscillation is started. This clock pulse is supplied only to the oscillation
settling counter (WDT) used to count the oscillation settling time.
After the elapse of the time set in the clock select bits (CKS[2:0]) in the watchdog timer
control/status register (WTCSR) of the WDT before the transition to software standby mode,
the WDT overflow occurs. Since this overflow indicates that the clock has been stabilized, the
clock pulse will be supplied to the entire chip after this overflow. Software standby mode is
thus cleared and NMI interrupt exception handling (IRQ interrupt exception handling in case
of IRRQ) is started. If the priority level of the generated interrupt is equal to or lower than the
interrupt mask level specified in the status register (SR) of the CPU, the interrupt request is not
accepted and software standby mode is not canceled.
When canceling software standby mode by the NMI interrupt or IRQ interrupt, set the
CKS[2:0] bits so that the WDT overflow period will be equal to or longer than the oscillation
settling time.
The clock output phase of the CKIO pin may be unstable immediately after detecting an
interrupt and until software standby mode is canceled. When software standby mode is
canceled by the falling edge of the NMI pin, the NMI pin should be high when the CPU enters
software standby mode (when the clock pulse stops) and should be low when software standby
mode is canceled (when the clock is initiated after oscillation settling). When software standby
mode is canceled by the rising edge of the NMI pin, the NMI pin should be low when the CPU
enters software standby mode (when the clock pulse stops) and should be high when software
standby mode is canceled (when the clock is initiated after oscillation settling). (The same
applies to the IRQ pin.)
When the RES pin is driven low, software standby mode is canceled and the LSI enters the
power-on reset state. After that, if the RES pin is driven high, the power-on reset exception
handling is started.
When the MRES pin is driven low, software standby mode is canceled and the LSI enters the
manual reset state. After that, if the MRES pin is driven high, the manual reset exception
handling is started.
Canceling Software Standby Mode
Rev. 3.00 Sep. 28, 2009 Page 1425 of 1650
Section 28 Power-Down Modes
REJ09B0313-0300