R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 854

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 16 Synchronous Serial Communication Unit (SSU)
16.4.6
When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is
cleared to 0, the SCS pin functions as an input (Hi-Z) to detect a conflict error. A conflict error
detection period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after
transfer ends. When a low level signal is input to the SCS pin within the period, a conflict error
occurs. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0.
Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0
Rev. 3.00 Sep. 28, 2009 Page 822 of 1650
REJ09B0313-0300
External input to SCS
Internal-clocked SCS
Internal signal for
Internal signal for
before resuming the transmission or reception.
transfer enable
transfer enable
SCS Pin Control and Conflict Error
SCS output
Figure 16.11 Conflict Error Detection Timing (After Transfer End)
Figure 16.10 Conflict Error Detection Timing (Before Transfer)
MSS
SCS
MSS
CE
Pφ
CE
(Hi-Z)
Transfer
end
detection period
Conflict error
Data written
to SSTDR
internally clocking SCS
(Hi-Z)
Worst time for
Conflict error detection
period