R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 806

KIT DEV FOR SH7203

R0K572030S000BE

Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K572030S000BE

Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Sep. 28, 2009 Page 774 of 1650
REJ09B0313-0300
Figure 15.8 Sample Flowchart for Receiving Serial Data (cont)
Read receive data in SCFRDR
and ORER flag in SCLSR to 0
Clear DR, ER, BRK flags
Overrun error handling
Receive error handling
Break handling
Error handling
ORER = 1?
in SCFSR,
BRK = 1?
ER = 1?
DR = 1?
End
Yes
Yes
Yes
Yes
No
No
No
No
• Whether a framing error or parity error
• When a break signal is received,
has occurred in the receive data that
is to be read from the receive FIFO
data register (SCFRDR) can be
ascertained from the FER and PER
bits in the serial status register
(SCFSR).
receive data is not transferred to
SCFRDR while the BRK flag is set.
However, note that the last data in
SCFRDR is H'00, and the break data
in which a framing error occurred is
stored.

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