R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 25

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 21 D/A Converter (DAC)....................................................................1045
21.1 Features .......................................................................................................................... 1045
21.2 Input/Output Pins ............................................................................................................. 1046
21.3 Register Descriptions ....................................................................................................... 1047
21.4 Operation ......................................................................................................................... 1050
21.5 Usage Notes ..................................................................................................................... 1051
Section 22 AND/NAND Flash Memory Controller (FLCTL) ........................1053
22.1 Features .......................................................................................................................... 1053
22.2 Input/Output Pins ............................................................................................................. 1057
22.3 Register Descriptions ....................................................................................................... 1058
22.4 Operation ......................................................................................................................... 1082
20.7.2
20.7.3
20.7.4
20.7.5
20.7.6
20.7.7
20.7.8
21.3.1
21.3.2
21.5.1
21.5.2
21.5.3
21.5.4
22.3.1
22.3.2
22.3.3
22.3.4
22.3.5
22.3.6
22.3.7
22.3.8
22.3.9
22.3.10 Ready Busy Timeout Counter (FLBSYCNT)................................................... 1078
22.3.11 Data FIFO Register (FLDTFIFO)..................................................................... 1079
22.3.12 Control Code FIFO Register (FLECFIFO) ....................................................... 1080
22.3.13 Transfer Control Register (FLTRCR)............................................................... 1081
22.4.1
Setting Analog Input Voltage ........................................................................... 1041
Notes on Board Design ..................................................................................... 1041
Processing of Analog Input Pins....................................................................... 1042
Permissible Signal Source Impedance .............................................................. 1043
Influences on Absolute Precision...................................................................... 1044
A/D Conversion in Deep Standby Mode .......................................................... 1044
Note on Usage in Scan Mode and Multi Mode................................................. 1044
D/A Data Registers 0 and 1 (DADR0 and DADR1)......................................... 1047
D/A Control Register (DACR) ......................................................................... 1048
Module Standby Mode Setting ......................................................................... 1051
D/A Output Hold Function in Software Standby Mode.................................... 1051
Setting Analog Input Voltage ........................................................................... 1051
D/A Conversion in Deep Standby Mode .......................................................... 1051
Common Control Register (FLCMNCR).......................................................... 1059
Command Control Register (FLCMDCR)........................................................ 1062
Command Code Register (FLCMCDR)............................................................ 1065
Address Register (FLADR) .............................................................................. 1066
Address Register 2 (FLADR2) ......................................................................... 1068
Data Counter Register (FLDTCNTR)............................................................... 1069
Data Register (FLDATAR)............................................................................... 1070
Interrupt DMA Control Register (FLINTDMACR) ......................................... 1071
Ready Busy Timeout Setting Register (FLBSYTMR) ..................................... 1077
Access Sequence............................................................................................... 1082
Rev. 3.00 Sep. 28, 2009 Page xxiii of xxx
REJ09B0313-0300