R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 35

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Items
Floating-point unit
(FPU)
Cache memory
Interrupt controller
(INTC)
Specification
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Floating-point co-processor included
Supports single-precision (32-bit) and double-precision (64-bit)
Supports data type and exceptions that conforms to IEEE754 standard
Two rounding modes: Round to nearest and round to zero
Two denormalization modes: Flush to zero
Floating-point registers
⎯ Sixteen 32-bit floating-point registers (single-precision × 16 words
⎯ Two 32-bit floating-point system registers
Supports FMAC (multiplication and accumulation) instructions
Supports FDIV (division) and FSQRT (square root) instructions
Supports FLDI0/FLDI1 (load constant 0/1) instructions
Instruction execution time
⎯ Latency (FAMC/FADD/FSUB/FMUL): Three cycles (single-
⎯ Pitch (FAMC/FADD/FSUB/FMUL): One cycle (single-precision), six
Five-stage pipeline
Instruction cache: 8 Kbytes
Operand cache: 8 Kbytes
128-entry/way, 4-way set associative, 16-byte block length
configuration each for the instruction cache and operand cache
Write-back, write-through, LRU replacement algorithm
Way-lock function available (only for operand cache); ways 2 and 3
can be locked
Seventeen external interrupt pins (NMI, IRQ7 to IRQ0, and PINT7 to
PINT0)
On-chip peripheral interrupts: Priority level set for each module
16 priority levels available
Register bank enabling fast register saving and restoring in interrupt
processing
or double-precision × 8 words)
precision), eight cycles (double-precision)
cycles (double-precision)
Note: FMAC only supports single-precision
Rev. 3.00 Sep. 28, 2009 Page 3 of 1650
Section 1 Overview
REJ09B0313-0300