R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 833

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

16.3.5
SSSR is a status flag register for interrupts.
Bit
7
6
5, 4
Bit Name
⎯
ORER
⎯
SS Status Register (SSSR)
Initial value:
Initial
Value
0
0
All 0
R/W:
Bit:
R/W
R
R/W
R
R
7
0
-
ORER
R/W
6
0
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Overrun Error
If the next data is received while RDRF = 1, an overrun
error occurs, indicating abnormal termination. SSRDR
stores 1-frame receive data before an overrun error
occurs and loses data to be received later. While ORER
= 1, consecutive serial reception cannot be continued.
Serial transmission cannot be continued, either. Note
that this bit has no effect during slave data receive
operation (MSS in SSCRH cleared to 0 and TE and RE
in SSER set to 0 and 1, respectively) in SSU mode
(SSUMS in SSCRL cleared to 0).
[Setting condition]
•
[Clearing condition]
•
Reserved
These bits are always read as 0. The write value should
always be 0.
R
5
0
-
Section 16 Synchronous Serial Communication Unit (SSU)
When one byte of the next reception is completed
with RDRF = 1 (except during slave data reception
in SSU mode)
When writing 0 after reading ORER = 1
R
4
0
-
TEND
R/W
3
0
Rev. 3.00 Sep. 28, 2009 Page 801 of 1650
TDRE
R/W
2
1
RDRF
R/W
1
0
R/W
CE
0
0
REJ09B0313-0300