R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 810

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

Section 15 Serial Communication Interface with FIFO (SCIF)

The data length is fixed at eight bits. No parity bit can be added.

An internal clock generated by the on-chip baud rate generator by the setting of the C/A bit in

SCSMR and CKE[1:0] in SCSCR, or an external clock input from the SCK pin can be selected as

the SCIF transmit/receive clock.

When the SCIF operates on an internal clock, it outputs the clock signal at the SCK pin. Eight

clock pulses are output per transmitted or received character. When the SCIF is not transmitting or

receiving, the clock signal remains in the high state. When only receiving, the clock signal outputs

while the RE bit of SCSCR is 1 and the number of data in receive FIFO is more than the receive

FIFO data trigger number.

• SCIF Initialization (Clock Synchronous Mode)

Rev. 3.00 Sep. 28, 2009 Page 778 of 1650

REJ09B0313-0300

Before transmitting, receiving, or changing the mode or communication format, the software

must clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the

SCIF. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing RE to 0,

however, does not initialize the RDF, PER, FER, and ORER flags and receive data register

(SCRDR), which retain their previous contents.

Transmit/Receive Formats

Transmitting and Receiving Data