R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 36

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 1 Overview
Rev. 3.00 Sep. 28, 2009 Page 4 of 1650
REJ09B0313-0300
Items
Bus state controller
(BSC)
Direct memory access
controller (DMAC)
Clock pulse generator
(CPG)
Watchdog timer
(WDT)
Specification
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Address space divided into eight areas (0 to 7), each a maximum of 64
Mbytes
The following features settable for each area independently
⎯ Bus size (8, 16, or 32 bits): Available sizes depend on the area.
⎯ Number of access wait cycles (different wait cycles can be
⎯ Idle wait cycle insertion (between same area access cycles or
⎯ Specifying the memory to be connected to each area enables
⎯ PCMCIA interface
⎯ Outputs a chip select signal (CS0 to CS7) according to the target
SDRAM refresh
Auto refresh or self refresh mode selectable
SDRAM burst access
Eight channels; external request available for four of them
Can be activated by on-chip peripheral modules
Burst mode and cycle steal mode
Intermittent mode available (16 and 64 cycles supported)
Transfer information can be automatically reloaded
Clock mode: Input clock can be selected from external input (EXTAL,
CKIO, or USB_X1) or crystal resonator
Input clock can be multiplied by 16 (max.) by the internal PLL circuit
Three types of clocks generated:
⎯ CPU clock: Maximum 200 MHz
⎯ Bus clock: Maximum 66 MHz
⎯ Peripheral clock: Maximum 33 MHz
On-chip one-channel watchdog timer
A counter overflow can reset the LSI
specified for read and write access cycles in some areas)
different area access cycles)
direct connection to SRAM, SRAM with byte selection, SDRAM,
and burst ROM (clocked synchronous or asynchronous). The
address/data multiplexed I/O (MPX) interface and burst MPX-I/O
interface are also available.
area (CS assert or negate timing can be selected by software)