R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 917

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Bit
6 to 4
3
2
1
0
Bit Name
CKDV[2:0]
MUEN
⎯
TRMD
EN
Initial
Value
000
0
0
0
0
R/W
R/W
R/W
R
R/W
R/W
Note:
Note: When mute is enabled, the serial data to be output
Description
Serial Oversampling Clock Division Ratio
Sets the ratio between oversampling clock* and the
serial bit clock. When the SCKD bit is 0, the setting of
these bits is ignored. The serial bit clock is used in the
shift register and is supplied from the SSISCK pin.
000: Serial bit clock frequency = Oversampling clock Frequency/1
001: Serial bit clock frequency = Oversampling clock frequency/2
010: Serial bit clock frequency = Oversampling clock frequency/4
011: Serial bit clock frequency = Oversampling clock frequency/8
100: Serial bit clock frequency = Oversampling clock frequency/16
101: Serial bit clock frequency = Oversampling clock frequency/6
110: Serial bit clock frequency = Oversampling clock frequency/12
111: Setting prohibited
Mute Enable
0: Module is not muted.
1: Module is muted.
Reserved
The read value is undefined. The write value should
always be 0.
Transmit/Receive Mode Select
0: Module is in receive mode.
1: Module is in transmit mode.
SSI Module Enable
0: Module is disabled.
1: Module is enabled.
is replaced with zeros, but data transfer within the
module does not stop. Therefore, dummy data
must be written to SSITRD to prevent a transmit
underflow from occurring.
* Oversampling clock is selected by the setting
of the SCSR bits in the PFC. For details, see
section 25, Pin Function Controller (PFC).
Rev. 3.00 Sep. 28, 2009 Page 885 of 1650
Section 18 Serial Sound Interface (SSI)
REJ09B0313-0300