R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1426

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

Section 27 On-Chip RAM

• Number of access cycles

Table 27.3 Number of Cycles for Access to On-Chip High-Speed RAM from the ID Bus

Note: For the settable ratios of Iφ to Bφ, see section 5, Clock Pulse Generator.

On-chip data retention RAM: The number of cycles required to read or write from the IC bus or

ID bus ranges from 1 Bφ + 2 Pφ (minimum) to 3 Pφ (maximum).

Rev. 3.00 Sep. 28, 2009 Page 1394 of 1650

REJ09B0313-0300

Each page of the on-chip high-speed RAM has two independent read and write ports and is

connected to the internal DMA bus (ID bus), CPU instruction fetch bus (F bus), and CPU

memory access bus (M bus). (Note that the F bus is connected only to the read ports.)

The F bus and M bus are used for access by the CPU, and the ID bus is used for access by the

The on-chip RAM for data retention has one read/write port and is connected to the peripheral

When the same page of the on-chip high-speed RAM is accessed from different buses

simultaneously, the access is processed according to the priority. The priority is ID bus > M

bus > F bus.

On-chip high-speed RAM: the number of cycles for access to read or write from buses F and I

is one cycle of Iφ. Number of cycles for access from the ID bus depend on the ratio of the

internal clock (Iφ) to the bus clock (Bφ). Table 27.3 indicates number of cycles for access from

Ratio of Iφ and Bφ

Number of Access (Bφ) Cycles