R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 394

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

Section 9 Bus State Controller (BSC)

SRAM Interface with Byte Selection

The SRAM interface with byte selection is for access to an SRAM which has a byte-selection pin

(WEn). This interface has 16-bit data pins and accesses SRAMs having upper and lower byte

selection pins, such as UB and LB.

When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the SRAM

interface with byte selection is the same as that for the normal space interface. While in read

access of a byte-selection SRAM interface, the byte-selection signal is output from the WEn pin,

which is different from that for the normal space interface. The basic access timing is shown in

figure 9.36. In write access, data is written to the memory according to the timing of the byte-

selection pin (WEn). For details, please refer to the Data Sheet for the corresponding memory.

If the BAS bit in CSnWCR is set to 1, the WEn pin and RD/WR pin timings change. Figure 9.37

shows the basic access timing. In write access, data is written to the memory according to the

timing of the write enable pin (RD/WR). The data hold timing from RD/WR negation to data write

must be acquired by setting the HW1 and HW0 bits in CSnWCR. Figure 9.38 shows the access

timing when a software wait is specified.

Rev. 3.00 Sep. 28, 2009 Page 362 of 1650

REJ09B0313-0300