R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1241

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

(3)
(a)
For pipes 1 to 7, the FIFO port can be accessed using the DMAC. When accessing the buffer for
the pipe targeted for DMA transfer is enabled, a DMA transfer request is issued.
The unit of transfer to the FIFO port should be selected using the MBW bit in DnFIFOSEL and
the pipe targeted for the DMA transfer should be selected using the CURPIPE bit. The selected
pipe should not be changed during the DMA transfer.
(b)
With this module, it is possible to complete FIFO data writing through DMA transfer by
controlling DMA transfer end signal input. A DMA transfer signal is output from the DMAC
when the number of DMA transfers specified in the DMA transfer count register (DMATCR) has
been performed. When a DMA transfer end signal is sampled, the module enables buffer memory
transmission (the same condition as when BVAL = 1). The TENDE bit in DnFBCFG can be used
to specify whether a DMA transfer end signal is sampled or not.
(c)
With this module, it is possible to add and send one zero-length packet after all of the data has
been sent, under the condition below, by setting 1 to the DEZPM bit in DnFIFOSEL. This
function can be set only if the buffer memory writing direction has been set (a pipe in the sending
direction has been set for the CURPIPE bits).
• If the number of data bytes written to the buffer memory is a multiple of the integer for the
(d)
If 1 is set for the DCLRM bit in DnFIFOSEL, the module automatically clears the buffer memory
of the corresponding pipe when reading of the data from the buffer memory has been completed.
Table 23.21 shows the packet reception and buffer memory clearing processing for each of the
various settings. As shown, the buffer clear conditions depend on the value set to the BFRE bit.
Using the DCLRM bit eliminates the need for the buffer to be cleared by software even if a
situation occurs that necessitates clearing of the buffer. This makes it possible to carry out DMA
transfers without involving software.
This function can be set only in the buffer memory reading direction.
maximum packet size when a DMA transfer end signal is sampled.
DMA Transfers (D0FIFO/D1FIFO port)
Overview of DMA Transfers
Auto Recognition of DMA Transfer Completion
Zero-Length Packet Addition Mode (D0FIFO/D1FIFO Port Writing Direction)
DnFIFO Auto Clear Mode (D0FIFO/D1FIFO Port Reading Direction)
Section 23 USB 2.0 Host/Function Module (USB)
Rev. 3.00 Sep. 28, 2009 Page 1209 of 1650
REJ09B0313-0300