R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1098

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 22 AND/NAND Flash Memory Controller (FLCTL)
22.3.4
FLADR is a 32-bit readable/writable register that specifies an address to be output. The address of
the size specified by the command control register is output sequentially from ADR1 in byte units.
With the sector access address specification bit (ADRMD) in the command control register, it is
possible to specify whether the sector number set in the address data bits is converted into an
address to be output to the flash
• ADRMD = 1
Initial value:
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 1066 of 1650
REJ09B0313-0300
Bit
31 to 24 ADR4[7:0]
23 to 16 ADR3[7:0]
15 to 8
7 to 0
R/W:
R/W:
Bit:
Bit:
Address Register (FLADR)
R/W
R/W
Bit Name
ADR2[7:0]
ADR1[7:0]
31
15
0
0
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
All 0
All 0
All 0
All 0
R/W
R/W
28
12
ADR4[7:0]
0
ADR2[7:0]
0
memory.
R/W
R/W
27
11
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
26
10
0
0
Description
Specify 4th data to be output to flash memory as an
address when ADRMD = 1.
Specify 3rd data to be output to flash memory as an
address when ADRMD = 1.
Specify 2nd data to be output to flash memory as an
address when ADRMD = 1.
Specify 1st data to be output to flash memory as an
address when ADRMD = 1.
Fourth Address Data
Third Address Data
Second Address Data
First Address Data
R/W
R/W
25
0
9
0
R/W
R/W
24
0
8
0
R/W
R/W
23
0
7
0
R/W
R/W
22
0
6
0
R/W
R/W
21
0
5
0
R/W
R/W
20
ADR3[7:0]
0
4
ADR1[7:0]
0
R/W
R/W
19
0
3
0
R/W
R/W
18
0
2
0
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0