R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1094

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 22 AND/NAND Flash Memory Controller (FLCTL)
22.3.2
FLCMDCR is a 32-bit readable/writable register that issues a command in command access mode,
specifies address issue, and specifies source or destination of data transfer. In sector access mode,
FLCMDCR specifies the number of sector transfers.
Initial value:
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 1062 of 1650
REJ09B0313-0300
Bit
31
30 to 27
R/W:
R/W:
Bit:
Bit:
CNT2
Command Control Register (FLCMDCR)
ADR
R/W
R/W
31
15
Bit Name
ADRCNT2 0
SCTCNT
[19:16]
0
0
R/W
R/W
30
14
0
0
SCTCNT[19:16]
R/W
R/W
29
13
0
0
Initial
Value
All 0
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
R/W
R
R/W
R/W
R/W
ADR
MD
26
10
0
0
Description
Specifies the number of bytes for the address data to
be issued in address stage. This bit is used together
with ADRCNT[1:0].
0: Issue the address of byte count, specified by
1: Issue 5-byte address. ADRCNT[1:0] should be set
Sector Transfer Count Specification [19:16]
These bits are extended bits of the sector transfer count
specification bits (SCTCNT) 15 to 0.
SCTCNT[19:16] and SCTCNT[15:0] are used together
to operate as SCTCNT[19:0], the 20-bit counter.
Address Issue Byte Count Specification 2
R/W
R/W
CDS
RC
25
0
9
0
ADRCNT[1:0].
to 00.
DOSR
SCTCNT[15:0]
R/W
R/W
24
0
8
0
R/W
23
R
0
7
0
-
R/W
22
R
0
6
0
-
R/W
R/W
SEL
RW
21
0
5
0
R/W
R/W
DOA
20
DR
0
4
0
ADRCNT[1:0]
R/W
R/W
19
0
3
0
R/W
R/W
18
0
2
0
R/W
R/W
DOC
MD2
17
0
1
0
R/W
R/W
DOC
MD1
16
0
0
0