R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1467

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

28.4.3
• After (1) power-on reset by RES pin is released, (2) the LSI transit to deep standby mode in
Table 28.5 Power-On Reset Exception Handling
• After (1) power-on reset by RES pin is released, (2) the LSI transit to deep standby mode, and
Address where
the program counter (PC) is fetched
H'FFFF8000
case that bit 6 (RAMBOOT) of deep standby control register 2 (DSCTR2) is set to "1", (3) the
deep standby mode is cancelled, and (4) power-on reset by WDT or H-UDI reset is occurred
before power-on reset by RES pin is executed again, then the behavior of the power-on reset
exception handling is as table 28.5. So if applicable as above case, PC and SP are necessary to
be retained in the area of on-chip RAM for data retention.
(3) the deep standby mode is cancelled, if there is a possibility that power-on reset by WDT or
H-UDI reset is occurred before power-on reset by RES pin is executed again, the settings of
WDT or H-UDI should be done in the condition that bit 15 (IOKEEP) and bits 9~0 of deep
standby cancel source flag register (DSFR) are all cleared after canceling deep standby mode
(if some bits are 1, please write these as “0”).
If (1) the setting of WDT or H-UDI is done in the condition that IOKEEP bit is not 0, and (2)
power-on reset by WDT or H-UDI reset is occurred before power-on reset by RES pin is
executed again, the pin status of the pins, whose pin status are retained in deep standby mode
and which are not in table 28.4, are kept retained. Additionally, in the case that bit 7
(CS0KEEPE) of deep standby control register 2 (DSCTR2) are set to “1”, the pin status of the
pins in table 28.4 are also keep retained.
If (1) the settings of WDT or H-UDI is done in the condition that bits 9~0 are not all 0, and (2)
power-on reset by WDT or H-UDI reset is occurred before power-on reset by RES pin is
executed again, the internal information about the deep standby canceling source is not
cleared, and deep standby mode are cancelled by the wrong canceling source when the LSI
attempt to transit to deep standby mode since then.
Notice about Power-On Reset Exception Handling
Address where
the stack pointer (SP) is fetched
H'FFFF8004
Rev. 3.00 Sep. 28, 2009 Page 1435 of 1650
Section 28 Power-Down Modes
REJ09B0313-0300