R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 437

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Bit
20
19
Bit Name
TEMASK
HE
Initial
Value
0
0
R/W
R/W
R/(W)*
1
Description
TE Set Mask
Specifies that DMA transfer does not stop even if the
TE bit is set to 1. If this bit is set to 1 along with the bit
for SAR/DAR reload function, DMA transfer can be
performed until the transfer request is cancelled.
In auto request mode or when a rising/falling edge of
the DREQ signal is detected in external request mode,
the setting of this bit is ignored and DMA transfer
stops if the TE bit is set to 1.
Note that this function is enabled only when either the
RLDSAR bit or the RLDDAR bit is set to 1.
0: DMA transfer stops if the TE bit is set
1: DMA transfer does not stop even if the TE bit is set
Half-End Flag
This bit is set to 1 when the transfer count reaches
half of the DMATCR value that was specified before
transfer starts.
If DMA transfer ends because of an NMI interrupt, a
DMA address error, or clearing of the DE bit or the
DME bit in DMAOR before the transfer count reaches
half of the initial DMATCR value, the HE bit is not set
to 1. If DMA transfer ends due to an NMI interrupt, a
DMA address error, or clearing of the DE bit or the
DME bit in DMAOR after the HE bit is set to 1, the bit
remains set to 1.
To clear the HE bit, write 0 to it after HE = 1 is read.*
0: DMATCR > (DMATCR set before transfer starts)/2
[Clearing condition]
•
1: DMATCR ≤ (DMATCR set before transfer starts)/2
during DMA transfer or after DMA transfer is
terminated
Writing 0 after reading HE = 1.*
Section 10 Direct Memory Access Controller (DMAC)
Rev. 3.00 Sep. 28, 2009 Page 405 of 1650
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REJ09B0313-0300
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