R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 809

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

In clock synchronous mode, the SCIF transmits and receives data in synchronization with clock

pulses. This mode is suitable for high-speed serial communication.

The SCIF transmitter and receiver are independent, so full-duplex communication is possible

while sharing the same clock. The transmitter and receiver are also 16-byte FIFO buffered, so

continuous transmitting or receiving is possible by reading or writing data while transmitting or

receiving is in progress.

Figure 15.11 shows the general format in clock synchronous serial communication.

Serial clock

In clock synchronous serial communication, each data bit is output on the communication line

from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of

the serial clock.

In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB

(last). After output of the MSB, the communication line remains in the state of the MSB.

In clock synchronous mode, the SCIF receives data by synchronizing with the rising edge of the

serial clock.

Note: * High except in continuous transfer

Operation in Clock Synchronous Mode

Figure 15.11 Data Format in Clock Synchronous Communication

One unit of transfer data (character or frame)

Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Sep. 28, 2009 Page 777 of 1650

REJ09B0313-0300