R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 789

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

15.3.10 FIFO Data Count Set Register (SCFDR)
SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data
register (SCFTDR) and the receive FIFO data register (SCFRDR).
It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of
receive data in SCFRDR with the lower 8 bits. SCFDR can always be read by the CPU.
Initial value:
Bit
0
Bit
15 to 13
12 to 8
7 to 5
4 to 0
R/W:
Bit:
Bit Name
LOOP
Bit Name
—
T[4:0]
—
R[4:0]
15
R
0
-
14
R
0
-
13
R
0
-
Initial
Value
0
Initial
Value
All 0
All 0
00000
00000
12
R
0
11
R
0
R/W
R/W
R/W
R
R
R
R
T[4:0]
10
R
0
Description
Loop-Back Test
Internally connects the transmit output pin (TxD) and
receive input pin (RxD) and internally connects the RTS
pin and CTS pin and enables loop-back testing.
0: Loop back test disabled
1: Loop back test enabled
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
T4 to T0 bits indicate the quantity of non-transmitted
data stored in SCFTDR. H'00 means no transmit data,
and H'10 means that SCFTDR is full of transmit data.
Reserved
These bits are always read as 0. The write value should
always be 0.
R4 to R0 bits indicate the quantity of receive data
stored in SCFRDR. H'00 means no receive data, and
H'10 means that SCFRDR full of receive data.
Section 15 Serial Communication Interface with FIFO (SCIF)
R
9
0
R
8
0
R
7
0
-
Rev. 3.00 Sep. 28, 2009 Page 757 of 1650
R
6
0
-
R
5
0
-
R
4
0
R
3
0
REJ09B0313-0300
R[4:0]
R
2
0
R
1
0
R
0
0