R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 45

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Classification
Operating mode
control
System control
Symbol
MD
MD_CLK1,
MD_CLK0
ASEMD
RES
MRES
WDTOVF
BREQ
BACK
I/O
I
I
I
I
I
O
I
O
Name
Mode set
ASE mode
Power-on reset
Manual reset
Watchdog timer
overflow
request
Bus-mastership
request
acknowledge
Clock mode set
Bus-mastership
Rev. 3.00 Sep. 28, 2009 Page 13 of 1650
Function
Sets the operating mode. Do not
change the signal level on this pin
during operation.
These pins set the clock operating
mode. Do not change the signal
levels on these pins during
operation.
If a low level is input at the ASEMD
pin while the RES pin is asserted,
ASE mode is entered; if a high level
is input, product chip mode is
entered.
In ASE mode, the E10A-USB
emulator function is enabled. When
this function is not in use, fix it high.
This LSI enters the power-on reset
state when this signal goes low.
This LSI enters the manual reset
state when this signal goes low.
Outputs an overflow signal from the
WDT.
A low level is input to this pin when
an external device requests the
release of the bus mastership.
Indicates that the bus mastership
has been released to an external
device. Reception of the BACK
signal informs the device which has
output the BREQ signal that it has
acquired the bus.
Section 1 Overview
REJ09B0313-0300