R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 906

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

Section 17 I

In master receive mode operation, set ACKBT before the falling edge of the 8th SCL cycle of the

last data being continuously transferred. Not doing so can lead to an overrun for the slave

transmission device.

When sequential bit-manipulation instructions are used to set the MST and TRS bits to select

master transmission in multi-master operation, a conflicting situation where AL in ICSR = 1 but

the mode is master transmit mode (MST = 1 and TRS = 1) may arise; this depends on the timing

of the loss of arbitration when the bit manipulation instruction for TRS is executed.

This can be avoided in either of the following ways.

• In multi-master operation, use the MOV instruction to set the MST and TRS bits.

• When arbitration is lost, check whether the MST and TRS bits are 0. If the MST and TRS bits

Rev. 3.00 Sep. 28, 2009 Page 874 of 1650

REJ09B0313-0300

have been set to a value other than 0, clear the bits to 0

Note on Setting ACKBT in Master Receive Mode

Note on the States of Bits MST and TRN when Arbitration Is Lost

C Bus Interface 3 (IIC3)